Aspects of the present invention relate generally to integrated circuit designs, and in particular to techniques for verification and debug of such designs.
Hardware designers, for example integrated circuit (IC) designers, do not always design every component of a new hardware device. While designers may design one or more components of a particular device, they often employ component designs (also known as intellectual property, or IP) from one or more third-party IP providers. Using components from third-party IP providers can facilitate the design by avoiding the need for the designer to design every aspect of the device's functionality.
Hardware designers may employ a hardware based verification platform to perform certain operations on a design. Hardware verification platforms can enable the presentation of real runtime scenarios occurring inside a component. Such presentations can facilitate design analysis and debugging. The designers can perform debugging operations to identify and fix defects that are encountered.
Conventionally, debug solutions involve running a debug program on the source code of the component(s) potentially causing the defect. Alternatively, a verification platform can provide a data dump of information for analysis to identify the cause of a defect. However, because many modern hardware devices utilize numerous components from multiple IP providers, simulating or stepping through the source code of every component to debug the design, or shifting through a data dump representing simulation information for the device components may not be feasible. Additionally, the source code of third-party components may be proprietary and inaccessible to a debug program.
Multiple aspects of the hardware typically may be tested during debug. For example, a hardware design may undergo architectural simulation and analysis and debugging where the functionality of each of the components being implemented in the design is tested, for example, with transaction level modeling (TLM) or bus functional modeling. The hardware design may additionally undergo circuit simulation and analysis where the signals between components are tested, for example using register transition level (RTL) analysis. Other steps may include system simulation, for example to model the components of a system together, and system and software emulation, for example to model execution of software elements executing on a modeled system. Each of these debugging methods typically utilizes different verification platforms and/or different interface tools, therefore there is limited crossover between verification methods and almost no reuse of tools or generated information across the different aspects of the verification process.
Accordingly, there is a need in the art for a system to efficiently debug and analyze components of a hardware design without accessing the source code of the components or other confidential or proprietary information. Additionally, there is a need in the art for a system that provides access to multiple aspects of the verification process within a single platform.